features ? high-speed access time: 8, 10, 12, 15, and 20 ns cmos low power operation ? 250 mw (typical) operating ? 250 w (typical) standby ttl compatible interface levels single 3.3v power supply fully static operation: no clock or refresh required three state outputs data control for upper and lower bytes industrial temperature available IS61LV6416 64k x 16 high-speed cmos static ram with 3.3v supply description the issi IS61LV6416 is a high-speed, 1,048,576-bit static ram organized as 65,536 words by 16 bits. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns with low power consumption. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs, ce and oe . the active low write enable ( we ) controls both writing and reading of the memory.a data byte allows upper byte ( ub ) and lower byte ( lb ) access. the IS61LV6416 is packaged in the jedec standard 44-pin 400-mil soj, 44-pin tsop, and 48-pin mini bga (6mm x 8mm). functional block diagram october 2000 issi reserves the right to make changes to its products at any time without notice in order to improve design and supply the be st possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2000, integrated silicon solution, inc. issi ? a0-a15 ce oe we 64k x 16 memory array decoder column i/o control circuit gnd vcc i/o data circuit i/o0-i/o7 lower byte i/o8-i/o15 upper byte ub lb integrated silicon solution, inc. 1 rev. d 10/20/00
IS61LV6416 2 integrated silicon solution, inc. rev. d 10/20/00 issi ? pin configurations 44-pin soj 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a15 a14 a13 a12 a11 ce i/o0 i/o1 i/o2 i/o3 vcc gnd i/o4 i/o5 i/o6 i/o7 we a10 a9 a8 a7 nc a0 a1 a2 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd vcc i/o11 i/o10 i/o9 i/o8 nc a3 a4 a5 a6 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a15 a14 a13 a12 a11 ce i/o0 i/o1 i/o2 i/o3 vcc gnd i/o4 i/o5 i/o6 i/o7 we a10 a9 a8 a7 nc a0 a1 a2 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd vcc i/o11 i/o10 i/o9 i/o8 nc a3 a4 a5 a6 nc 44-pin tsop 48-pin mini bga (6mm x 8mm) pin descriptions a0-a15 address inputs i/o0-i/o15 data inputs/outputs ce chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection vcc power gnd ground 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 n/c i/o 8 ub a3 a4 ce i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 nc a7 i/o 3 vcc vcc i/o 12 nc nc i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 nc a8 a9 a10 a11 nc
IS61LV6416 integrated silicon solution, inc. 3 rev. d 10/20/00 1 2 3 4 5 6 7 8 9 10 11 12 issi ? operating range range ambient temperature vcc(8,10ns) v cc (12,15,20 ns ) commercial 0 c to +70 c 3.3v+10%,-5% 3.3v 10% industrial ? 40 c to +85 c 3.3v+10%,-5% 3.3v 10% dc electrical characteristics (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 ? v v ol output low voltage v cc = min., i ol = 8.0 ma ? 0.4 v v ih input high voltage 2 v cc + 0.3 v v il input low voltage (1) ? 0.3 0.8 v i li input leakage gnd v in v cc ? 22a i lo output leakage gnd v out v cc , outputs disabled ? 22a notes: 1. v il (min.) = ? 2.0v for pulse width less than 10 ns. absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ? 0.5 to vcc+0.5 v t stg storage temperature ? 65 to +150 c p t power dissipation 1.5 w i out dc output current (low) 20 ma note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table i/o pin mode we ce oe lb ub i/o0-i/o7 i/o8-i/o15 vcc current not selected x h x x x high-z high-z i sb 1 , i sb 2 output disabled h l h x x high-z high-z i cc x l x h h high-z high-z read h l l l h d out high-z i cc h l l h l high-z d out hllll d out d out write l l x l h d in high-z i cc l l x h l high-z d in llxll d in d in
IS61LV6416 4 integrated silicon solution, inc. rev. d 10/20/00 issi ? read cycle switching characteristics (1) (over operating range) -8 ns -10 ns -12 ns -15 ns -20 ns symbol parameter min. max. min. max. min. max. min. max. min. max. unit t rc read cycle time 8 ? 10 ? 12 ? 15 ? 20 ? ns t aa address access time ? 8 ? 10 ? 12 ? 15 ? 20 ns t oha output hold time 3 ? 3 ? 3 ? 3 ? 3 ? ns t ace ce access time ? 8 ? 10 ? 12 ? 15 ? 20 ns t doe oe access time ? 5 ? 5 ? 6 ? 7 ? 8ns t hzoe (2) oe to high-z output ? 5 ? 5 ? 60608ns t lzoe (2) oe to low-z output 0 ? 0 ? 0 ? 0 ? 0 ? ns t hzce (2 ce to high-z output 0 4 0 5 0 6 0 6 0 8 ns t lzce (2) ce to low-z output 3 ? 3 ? 3 ? 3 ? 3 ? ns t ba lb , ub access time ? 6 ? 6 ? 6 ? 7 ? 8ns t hzb lb , ub to high-z output 0 4 0 5 0 6 0 6 0 8 ns t lzb lb , ub to low-z output 0 ? 0 ? 0 ? 0 ? 0 ? ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v and output loading specified in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested. capacitance (1) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf note: 1. tested initially and after any design or process changes that may affect these parameters. power supply characteristics (1) (over operating range) -8 ns -10 ns -12 ns -15 ns -20 ns symbol parameter test conditions min. max. min. max. min. max. min. max. min. max. unit i cc vcc dynamic operating v cc = max., com. ? 210 ? 190 ? 150 ? 130 ? 120 ma supply current i out = 0 ma, f = f max ind. ? 215 ? 210 ? 170 ? 150 ? 140 i sb 1 ttl standby current v cc = max., com. ? 25 ? 25 ? 15 ? 15 ? 15 ma (ttl inputs) v in = v ih or v il ind. ? 30 ? 30 ? 25 ? 25 ? 25 ce v ih , f = 0 i sb 2 cmos standby v cc = max., com. ? 10 ? 10 ? 10 ? 10 ? 10 ma current (cmos inputs) ce v cc ? 0.2v, ind. ? 15 ? 15 ? 15 ? 15 ? 15 v in v cc ? 0.2v, or v in 0.2v, f = 0 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS61LV6416 integrated silicon solution, inc. 5 rev. d 10/20/00 1 2 3 4 5 6 7 8 9 10 11 12 issi ? ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 3 ns input and output timing 1.5v and reference level output load see figures 1a and 1b ac test loads figure 1a. figure 1b. 319 ? 30 pf including jig and scope 353 ? output 3.3v 319 ? 5 pf including jig and scope 353 ? output 3.3v
IS61LV6416 6 integrated silicon solution, inc. rev. d 10/20/00 issi ? data valid read1.eps previous data valid t aa t oha t oha t rc d out address t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid t hzb address oe ce lb, ub d out t hzce t ba t lzb read cycle no. 2 (1,3) ac waveforms read cycle no. 1 (1,2) (address controlled) ( cs = oe = v il , ub or lb = v il ) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce , ub , or lb = v il . 3. address is valid prior to or coincident with ce low transition.
IS61LV6416 integrated silicon solution, inc. 7 rev. d 10/20/00 1 2 3 4 5 6 7 8 9 10 11 12 issi ? write cycle switching characteristics (1,3) (over operating range) -8 ns -10 ns -12 ns -15 ns -20 ns symbol parameter min. max. min. max. min. max. min. max. min. max. unit t wc write cycle time 8 ? 10 ? 12 ? 15 ? 20 ? ns t sce ce to write end 6 ? 8 ? 9 ? 10 ? 12 ? ns t aw address setup time 8 ? 8 ? 9 ? 10 ? 12 ? ns to write end t ha address hold from write end 0 ? 0 ? 0 ? 0 ? 0 ? ns t sa address setup time 0 ? 0 ? 0 ? 0 ? 0 ? ns t pwb lb , ub valid to end of write 7 ? 8 ? 9 ? 10 ? 12 ? ns t pwe we pulse width 6 ? 8 ? 9 ? 10 ? 12 ? ns t sd data setup to write end 6 ? 6 ? 6 ? 7 ? 9 ? ns t hd data hold from write end 0 ? 0 ? 0 ? 0 ? 0 ? ns t hzwe (2) we low to high-z output ? 4 ? 5 ? 6 ? 7 ? 9ns t lzwe (2) we high to low-z output 3 ? 3 ? 3 ? 3 ? 3 ? ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v and output loading specified in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and ub or lb , and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to t he rising or falling edge of the signal that terminates the write.
IS61LV6416 8 integrated silicon solution, inc. rev. d 10/20/00 issi ? notes: 1. write is an internally generated signal asserted during an overlap of the low states on the ce and we inputs and at least one of the lb and ub inputs being in the low state. 2. write = ( ce ) [ ( lb ) = ( ub ) ] ( we ). ac waveforms write cycle no. 1 ( we controlled) (1,2) undefined undefined t wc t sce t pwb t aw t ha high-z high-z t pwe t hd t sa t hzwe address ce lb, ub we write (1) d out d in t lzwe t sd
IS61LV6416 integrated silicon solution, inc. 9 rev. d 10/20/00 1 2 3 4 5 6 7 8 9 10 11 12 issi ? ordering information commercial range: 0c to +70c speed (ns) order part no. package 8 IS61LV6416-8b mini bga (6mm x 8mm) 8 IS61LV6416-8t plastic tsop 8 IS61LV6416-8k 400-mil plastic soj 10 IS61LV6416-10b mini bga (6mm x 8mm) 10 IS61LV6416-10t plastic tsop 10 IS61LV6416-10k 400-mil plastic soj 12 IS61LV6416-12b mini bga (6mm x 8mm) 12 IS61LV6416-12t plastic tsop 12 IS61LV6416-12k 400-mil plastic soj 15 IS61LV6416-15b mini bga (6mm x 8mm) 15 IS61LV6416-15t plastic tsop 15 IS61LV6416-15k 400-mil plastic soj 20 IS61LV6416-20b mini bga (6mm x 8mm) 20 IS61LV6416-20t plastic tsop 20 IS61LV6416-20k 400-mil plastic soj
IS61LV6416 10 integrated silicon solution, inc. rev. d 10/20/00 issi ? issi ? integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com www.issi.com ordering information industrial range: ?40c to +85c speed (ns) order part no. package 8 IS61LV6416-8bi mini bga (6mm x 8mm) 8 IS61LV6416-8ti plastic tsop 8 IS61LV6416-8ki 400-mil plastic soj 10 IS61LV6416-10bi mini bga (6mm x 8mm) 10 IS61LV6416-10ti plastic tsop 10 IS61LV6416-10ki 400-mil plastic soj 12 IS61LV6416-12bi mini bga (6mm x 8mm) 12 IS61LV6416-12ti plastic tsop 12 IS61LV6416-12ki 400-mil plastic soj 15 IS61LV6416-15bi mini bga (6mm x 8mm) 15 IS61LV6416-15ti plastic tsop 15 IS61LV6416-15ki 400-mil plastic soj 20 IS61LV6416-20bi mini bga (6mm x 8mm) 20 IS61LV6416-20ti plastic tsop 20 IS61LV6416-20ki 400-mil plastic soj
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